Computer-aided engineering (CAE) technology includes software tools that assist in the design and layout of the masks used in the production of integrated circuit chips (ICs) by photolithography. Chip design may begin with the creation of a schematic using a CAE drafting tool. This schematic is then translated into a netlist--a text file that describes all of the schematic's instances and their interconnecting nets.
The netlist can be used for several purposes. It may be input to a computerized simulator or verifier to test the circuit before its hardware implementation. Or the netlist can be input to a layout synthesis program. A layout synthesizer converts the netlist into a geometric circuit description by determining a "good" placement of the circuit's polygon regions by analyzing the connectivity and physical placement of the instances and their elementary regions. The synthesizer determines whether a group of transistors within the circuit can share source/drain regions. Another function of a synthesizer is to determine whether a transistor with a wide gate should be folded into a series of shorter gates having common source/drain regions.
After synthesizing the circuit design, a compactor can be used to produce the final layout of the regions. The compactor follows the set of design rules while determining the physical location of the source/drain, gate, and contact positions.
What is needed in the art is a CAE tool, to be called a "device generator". The device generator should be able to represent circuit devices as objects using an advanced symbolic device layout representation so that the devices (such as transistors, capacitors, and resistors) could be more readily manipulated. Modeling devices as objects in such a fashion could assist the synthesizer in placing complex series-parallel transistor structures. This would result in layout which is more compact than using individual transistors. Such a device generator would be used to construct layout for the integrated circuit transistor structures upon command from either the synthesizer or engineer and would write out the resulting layout of the polygon regions to the appropriate layout database directly as opposed to relying on the compactor to subsequently perform the layout. Unlike a compactor, which places all of the device regions at a single time, what is needed is a device generator allowing placement to be done repetitively. During the layout synthesis process, each portion of the circuit could be separately placed. This would allow the layout synthesizer to rely on a previously placed portion of the circuit for its remaining placement.
This device generator would need to follow design rules and be able to control gate widths and lengths while still allowing for merging of active area regions between transistor gates. It should give a fast response to the layout creation process and be able to regenerate portions of the layout upon command.